1. Field of the Invention
The present invention relates to a semiconductor, and more particularly to a substrate voltage generator for a semiconductor which prevents a substrate voltage from being generated at an abnormally extreme level.
2. Discussion of the Background
In a semiconductor device receiving initial power-up voltage, a substrate voltage generator is required to supply a stable substrate voltage up to a predetermined level.
FIG. 1 schematically illustrates a typical substrate voltage generator. As shown therein, a conventional substrate voltage generator 1 supplies a desired substrate voltage V.sub.BB with the start of power-up detection.
The substrate voltage generator 1, connected with a power supply detector 2, receives a detection signal at a predetermined level supplied from the power supply detector 2 in accordance with the power-up. The substrate voltage generator 1 is composed of a controller 11, an oscillator 12 and a pump circuit 13. The substrate voltage V.sub.BB is outputted from the pump circuit 13 as a final output.
With reference to FIGS. 2A through 2C, an operation of the substrate voltage generator 1 will be described.
First, the start of power-up is informed by which a level of an externally applied power supply voltage Vcc is detected by the power supply detector 2, and the power supply detector 2 at a high level is transited to a low level, as shown in FIG. 2A, and informs the transit point by a reset signal. The power supply voltage Vcc is gradually increased up to a predetermined level in accordance with the power-up, and the power supply detector 2 detects the predetermined level and thus generates the reset signal.
The thusly generated reset signal is applied to the controller 11 of the substrate voltage generator 1. The controller 11 supplies an oscillator enable signal OSCEN, which was transited to a high level at the point where the reset signal was generated, as shown in 2B, to the oscillator 12. The controller 11 which controls the operation of the oscillator 12 to obtain the desired substrate voltage V.sub.BB level is constructed to sense the level of the substrate voltage V.sub.BB.
The oscillator 12 corresponds to the signal supplied from the controller 11 and generates an oscillation signal OSC which has a predetermined cycle. The oscillation signal OSC from the oscillator 12 is supplied to the pump circuit 13 which will generate the substrate voltage V.sub.BB, as shown in FIG. 2C. Since the initial level of the substrate voltage V.sub.BB is considerably different from the desired value, the substrate voltage generator 1 operates so that the substrate voltage V.sub.BB is sensed by the controller 11, for thus obtaining the desirable voltage level.
When the substrate voltage V.sub.BB level reaches the desired value, the oscillator enable signal OSCEN supplied from the controller 11 is outputted at a low level, as shown in FIG. 2B, for thereby completing the operation of the substrate voltage generator 1.
In the conventional art, however, when the level of the externally applied power supply voltage Vcc is high, or a substrate voltage loading is small, for example when the substrate voltage V.sub.BB is pumped at an extreme level because the driving capability of pumping for generating the substrate voltage V.sub.BB is great, the substrate voltage V.sub.BB level may not be controlled. In such a case, as shown in FIG. 2C, the final level of the substrate voltage V.sub.BB may be reached faster than the designed arrival time allated for the substrate voltage to reach the desired level. This unwanted situation may cause erroneous operations in other voltage generators of the chip device, and particularly become the cause of reference voltage generators being faulty. In other words, an erroneous operation of the substrate voltage generator in the initial power-up for the semiconductor device may change the reference voltage, due to the substrate voltage level being too low or too high.
Similarly, when a precharge voltage V.sub.BLP with respect to bit lines or a cell plate voltage V.sub.CP in a semiconductor memory device has an abnormally high or low level, the substrate voltage varies due to an erroneous operation related to other factors which are operated with the relation to the voltage level, and thus the entire semiconductor device may have operational problems.